Defect Analysis for Delay-Fault BIST in FPGAs

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of Look-Up Tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption – the propagation delay of a LUT is independent of the function realized by it considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA. List of keywords: BIST, FPGA, Delay Testing Suggested topic: BIST The authors want the paper to be considered for publication in the Symposium Proceedings. Corresponding Author: Dr. Patrick GIRARD Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II / CNRS 161 rue Ada, 34392 Montpellier Cedex 5 FRANCE Tél. : (+33) 467 41 86 29 Fax : (+33) 467 41 85 00 Email : [email protected]